Search - vhdl uart

[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL

Description: 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
Platform: | Size: 10240 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] conv_code

Description: 用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3)- Convolutional Codes.
Platform: | Size: 1024 | Author: 武汉 | Hits:

[Com Port] uart_VHDL

Description: uart的vhdl实现代码分模块设计和状态机设计不错的，用它没错-UART achieve the VHDL code modular design and state machine design good, the right to use it
Platform: | Size: 10240 | Author: 王平 | Hits:

[Windows Develop] edaeda

Description: 完整的串行通信电路vhdl代码，已经通过quartus4.0编译-complete serial communication circuit VHDL code, the compiler has passed quartus4.0
Platform: | Size: 1024 | Author: 鲁东旭 | Hits:

[VHDL-FPGA-Verilog] ISE_uart

Description: 自己在ISE下用VHDL写的UART，简单，易懂-in ISE using VHDL was the UART, simple, understandable
Platform: | Size: 936960 | Author: sk | Hits:

[VHDL-FPGA-Verilog] vhdl-2

Description:
Platform: | Size: 59392 | Author: lileiming | Hits:

[VHDL-FPGA-Verilog] Exp6-VGA

Description: 通过UART从PC主机读取图片数据，并完成图片在VGA显示器上的显示-through UART from the host PC to read image data, and complete picture of the VGA display on the show
Platform: | Size: 681984 | Author: 萧飒 | Hits:

[Process-Thread] UART

Description: minimum uart Image for transfer image to FPGA then read again by PC
Platform: | Size: 409600 | Author: umar | Hits:

[VHDL-FPGA-Verilog] Uart

Description: Uart总线，VHDL语言，硬件描述语言源码-Uart bus, VHDL language, VHDL source code
Platform: | Size: 10240 | Author: 陳皇仁 | Hits:

Description: 包含一个在QUARYUS环境下运行的UART的工程，实际在EP2C20Q240上调试成功的通用串口VHDL程序-The QUARYUS environment contains a UART to run the project, the actual success of the EP2C20Q240 Universal Serial debugging VHDL programs
Platform: | Size: 2151424 | Author: 王果 | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart串口通信程序，用状态机实现的；测试通过，并且实践过-uart
Platform: | Size: 787456 | Author: dasfsaf | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart-universal aynchronious reciever and transmitter used to connect the pc and fpga to pass the data
Platform: | Size: 3072 | Author: priya | Hits:

[VHDL-FPGA-Verilog] uart-vhdl-testbench

Description: simple uart vhdl behavioural model (package) vhdl testbench example
Platform: | Size: 2048 | Author: Mark | Hits:

[Embeded-SCM Develop] UART

Description: A simple preoteus based design to display the characters typed int the keyboard into LCD using UART of 8051.Plz make sure that TTL to RS232 is inserted in between the microcontroller and virtual terminal which is not shown in the design.
Platform: | Size: 45056 | Author: sandeep | Hits:

[VHDL-FPGA-Verilog] uart

Description: FPGA中的UART模块，调试通过的哦！！希望对大家有所帮助，呵呵。。。我用的是quartus7.2版本编写的，当然也有些copy网上的-FPGA in the UART modules, debugging through the Oh! ! We want to help, Hehe. . . I use the quartus7.2 version of the written, of course, also some copy online
Platform: | Size: 1766400 | Author: 单子奇 | Hits:

[Other] uart

Description: UART串口的VHDL源程序，希望对大家有用-UART serial port of the VHDL source code, we want to be useful
Platform: | Size: 17408 | Author: 贾明 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 采用VHDL语言编写的串口驱动程序，已调试通过，能够实现同PC机的数据传输，可读性好，可移植性好-VHDL language using the serial driver has been debugged, to achieve the same PC, the data transmission, readable and portable
Platform: | Size: 526336 | Author: 王玉强 | Hits:

[VHDL-FPGA-Verilog] UART

Description: FPGA的UART程序，非常好的，讲解详细，我当初看了好多都看不懂，看了这个以后终于明白-FPGA' s UART program, very good, detailed explanation, I had read a lot have not read, finally realized after reading this
Platform: | Size: 276480 | Author: xuxing | Hits:

[VHDL-FPGA-Verilog] UART

Description: xilinx官网提供的VHDL,UART串行通信模块，肯定好用，官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official
Platform: | Size: 10240 | Author: 雪尘 | Hits:

[VHDL-FPGA-Verilog] uart

Description: VHDL实现串口转换的代码，串行通信的发送器有五个状态：--1.X_IDLE(空闲)状态 : 当UART被复位后,状态机将立刻进入这一状态,在这个状态下, -- 状态机一直等待发送命令XMIT_CMD,当接收到发送命令后,状态机进入X_START状态,准备发送起始位信号 --2.X_START状态 : 在这个状态下,UART发送一个位时间宽度的逻辑'0',信号至TXD,即 -- 起始位,紧接着状态机进入X_SHIFT状态,发一位数据 --3.X_WAIT状态 : 当状态机处于这一个状态时,等待计满15个bclk周期,在第16个bclk进入X_SHIFT状态 -- 进行数据位的发送,同时也判断发送的数据位长度是否已经达到数据帧的长度,如果 = framlent,就说明 -- 停止位发送进入停止状态. --4.X_SHIFT状态 : 实现待发数据的并串转换,转换完成立即进入X_WAIT状态,进行下一次发送 --5.X_STOP状态 : 停止位发送,当数据帧发送完毕后,状态机进入该状态,并发送16个bclk周期的逻辑1信号, -- 即1位停止位.然后进入X_IDLE状态,并等待另一个数据帧发送命令(VHDL serial port conversion code)
Platform: | Size: 480256 | Author: 辉耀丿城主 | Hits:

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[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL

[VHDL-FPGA-Verilog] conv_code

[Com Port] uart_VHDL

[Windows Develop] edaeda

[VHDL-FPGA-Verilog] ISE_uart

[VHDL-FPGA-Verilog] vhdl-2

[VHDL-FPGA-Verilog] Exp6-VGA

[Process-Thread] UART

[VHDL-FPGA-Verilog] Uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart-vhdl-testbench

[Embeded-SCM Develop] UART

[VHDL-FPGA-Verilog] uart

[Other] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

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